The present invention relates to a self-aligned, low dielectric constant gate cap and a method of forming the same.
Integrated circuits can comprise a large number of circuit elements such as transistors. While significant progress has been made over recent decades with respect to increased performance and reduced feature size of circuit elements, there is an ongoing demand for enhanced functionality of electronic devices, a continuous desire to reduce the dimensions of the circuit elements, and a desire to continue to increase the operating speed of the circuit elements.
With continuous transistor scaling, gate-to-drain and gate-to-source capacitance increases due to the increased proximity of the source and drain metallization contacts (vias) to the gate conductor. For instance, the distance between the contact via and the gate conductor can be as little as 40 nanometers or less in dense logic circuits. With misalignment of the contact via with respect to the gate, the spacing between the gate and the via can be significantly less than 40 nm. To make matters worse, due to Miller effect, the capacitance between the gate and drain via is multiplied by the gain of the complementary metal oxide semiconductor stage.
As a result, the total gate-to-drain and gate-to-source capacitance becomes a significant portion of the overall load capacitance for fast, lightly loaded semiconductor circuits with transistors fabricated, for example, in 7 nm technology and below. By reducing the total gate-to-drain and gate-to-source capacitance, a significant leverage in increasing circuit speed can be realized.
In view of the above, there is still a need for providing a self-aligned gate cap with a reduced capacitance.